The advancement of the integrated circuit technology has enabled millions of memory cells to be fabricated on a single semiconductor chip. This is admittedly a much desired achievement in view of the traditional magnetic core-type of memories which were both slow and required substantial physical space. However, the magnetic core memories were nonvolatile, i.e., the cells maintained an electrical state even when power was removed from the unit, whereas the semiconductor dynamic random access memories (DRAMs) and static random access memories (SRAMs) are generally of the volatile type where all of the data information is lost when power is removed from the chips. Although the packaging density of DRAM cells is high due to the single transistor configuration, currently up to 4 or 16 megabit per chip, the cells require refresh every 10-15 milliseconds to restore the charge on the cell capacitors. With this frequency of refresh, there is required either on or off-chip circuitry dedicated to such refresh operations.
In response to a need for nonvolatile semiconductor memories, there have been developed semiconductor memories known as an electrical programmable read only memory (EPROM), and an electrically erasable programmable read only memory (EEPROM). These nonvolatile semiconductor memories can indeed maintain the stored information when the power is removed from the devices, but such devices normally have much slower write speeds and require high voltage write circuits. Also, such memory devices are useful for a limited number of write operations as the nonvolatile storage mechanism decays as a function of the number of times the cell is written. The mechanism by which such nonvolatile storage is made possible is the formation of an electron tunnel charge in a transistor gate area of the cell, which charge remains irrespective of the supply voltage applied to the cell.
Another type of nonvolatile memory is the battery-backed SRAM. This type of memory generally has a six-transistor cell with a miniature battery molded in the package encapsulant. Although power remains on the chip when the package is removed from its socket, the memory arrays cannot be made large due to the number of transistors required per cell.
In the recent development of nonvolatile semiconductor memories, ferroelectric materials have been utilized as a storage mechanism for each cell. Particularly, a ferroelectric capacitor can be polarized with a specified state, which state can be maintained even in the absence of a voltage applied to the cell. One substantial advantage of the use of ferroelectric capacitive elements in the memory cells is that the packaging densities approach that of semiconductor DRAM memories, and the read and write speeds are also comparable. However, a major disadvantage of the use of ferroelectric material in memories is that there exists a gradual loss of detectable ferroelectric polarization as a result of repeated switching due to normal read and write operations of the cell. It is apparent, therefore, that even though the packaging density and write speeds of ferroelectric memory cells represent a significant improvement over prior EPROMs and EEPROMs, the useful life of the ferroelectric memories is still limited, albeit due to a different electrical mechanism.
From the foregoing, it can be seen that a need exists for a technique to extend the endurance of ferroelectric-type capacitors. A further need exists for methods and apparatus for reading and writing ferroelectric memories in such a manner as to extend the life thereof, well beyond that of present-day nonvolatile semiconductor memories. Another need exists for a ferroelectric memory having circuitry adapted for refreshing each of the capacitors in the array.